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This chapter looks at the question of managing multiple phases in a
scheduled router. It starts with a discussion of the `continuing operators'
that traverse phases in Section 5.1.
Section 5.2 discusses how to ensure all
the data I/O is complete before changing phase, and Section 5.3
explores the restrictions placed on wire usage by consecutive phases.
Section 5.4 discusses how to allocate router memory to
the various phases, and Section 5.5 presents an algorithm
for associating phase loads with operator load functions.
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